`timescale 1ns / 1ps
//Name: Robert Smith
//PID: A08609119
//Name: Shreenidhi Chowkwale
//PID: A09089080
//
// CSE141L Lab 2, Part 1: Fetch Datapath
// University of California, San Diego
// 
// Written by Donghwan Jeon, 4/10/2007
// Updated by Sat Garcia, 4/8/2008
// Updated by Michael Taylor, 4/4/2011z

// 2 input Adder Module
//
// parameters:
// 	WIDTH: data width for inputs and output
//
module adder#(parameter WIDTH=10)
(
	input		[WIDTH-1:0] d0_i,
	input		[WIDTH-1:0] d1_i,
	output	[WIDTH-1:0] d_o
);
	
	assign d_o = d0_i + d1_i;
endmodule
